1. Field of the Invention
The present disclosure generally relates to semiconductor devices, and, more particularly, to devices having gate and channel lengths smaller than 35 nm and to fabricating according semiconductor devices.
2. Description of the Related Art
The majority of present-day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs) or simply MOS transistors. Typically, present-day integrated circuits are implemented by millions of MOS transistors which are formed on a semiconductor substrate with a given surface area.
Basically, MOS transistors act as electronic switching elements wherein a current through a channel region, formed between source and drain regions of a MOS transistor, is controlled by a gate electrode which is typically disposed over the channel region, independent from whether a PMOS transistor or an NMOS transistor is considered. Particularly, the conductivity state of a transistor is changed by a voltage applied to the gate electrode passing a so-called threshold voltage (Vt). In general, the threshold voltage depends nontrivially on the transistor's properties, such as size, material, etc.
However, as semiconductor devices and device features have become smaller in order to comply with requirements set by advanced integration densities, conventional fabrication techniques have been pushed to their limits, challenging their abilities to produce finely defined features at presently required scales. Consequently, developers are faced anew at each scale with problems and constraints imposed by scaling limitations which arise as semiconductor devices continue to decrease in size.
Typically, high-k gate dielectric materials are very sensitive to manufacturing environments, such as high temperatures, conventionally present during annealing sequences necessary for healing crystal damages caused by implantations and activation of implanted impurities, and cleaning and etching environments, which are, for example, present in various cleaning and etching processes applied at various stages during fabrication.
In conventional gate first processes in which a gate stack comprising a gate dielectric and a gate electrode material layer formed on the gate dielectric is implemented at an early stage of fabrication, particularly before formation of source and drain regions, a thick encapsulation spacer having a thickness of about 125 Å and, for example, consisting of silicon nitride is necessary to reliably encapsulate the gate dielectric. This is conventionally achieved by depositing a silicon nitride layer having a thickness of 45 Å in a molecular layer deposition (MLD) and a subsequent deposition of further 80 Å of silicon nitride material by a low pressure chemical vapor deposition (LPCVD) process or a rapid thermal chemical vapor deposition (RTCVD) process. Consequently after performing source/drain extension region implantation sequences for forming source/drain extension regions in alignment with the previously formed spacer encapsulation, extension regions are formed at more than 13 nm away from a channel region, wherein the channel region is disposed directly under the gate stack within the semiconductor substrate. It turned out that, in order to diffuse a sufficient amount of dopants towards the channel region under the spacer encapsulation, it is necessary to implant source/drain implantation species to a depth of about 20 nm into the semiconductor substrate such that, during a subsequent annealing process, a sufficient amount of dopants is driven sufficiently deep under the spacer forming a sufficiently small channel region under the gate stack.
However, in advanced semiconductor devices fabricated with ultra large scale integration (ULSI) techniques giving ultra-small gate lengths or channel lengths, it is required to implant source/drain extension dopants into a depth of about 10 nm, thus setting an upper constraint on a maximum spacer thickness for encapsulation spacers of about 5 nm, opposed to conventional spacer thickness of 13 nm which is required for reliable encapsulation of complex gate dielectric materials. Current propositions are directed to additionally increase the halo doses, which further leads to performance drawbacks for advanced semiconductor devices.
It is, therefore, desirable to provide a method which allows for reliably encapsulating gate dielectric materials at an early stage of fabrication and particularly before formation of source/drain extension regions without increasing a halo implantation dose and implantation depth of source/drain extension dopants. Furthermore, it is desirable to provide a semiconductor device having a reliably encapsulated gate dielectric, particularly at least improving, if not avoiding, at least some of the above-discussed problems.